(1) Field of the Invention
The present invention relates to a memory system including a plurality of memory modules such as memory sub-systems, particularly to a memory system comprising a plurality of memory units in the respective memory modules.
(2) Description of the Related Art
As this type of memory system, there has heretofore been a DRAM memory system comprising a constitution in which a plurality of memory modules are attached onto a mother board and these memory modules are controlled by a chip set (memory controller) and a plurality of DRAMs are mounted as memory units on the respective memory modules.
For the above-described DRAM memory system, a system has been proposed in which a stub series terminated transceiver logic (SSTL) is used as interface standards and data can be written/read at a high rate and with a low signal amplitude using a double data rate (DDR) method for inputting/outputting data in synchronization with front and rear edges of a clock.
As an example of this memory system, a memory system including a plurality of memory modules (i.e., DRAM modules) on which a plurality of DRAMs are mounted and which are attached to a mother board has been described in Japanese Patent Application Laid-Open No. 2001-256772 (hereinafter referred to as Patent Document 1). Specifically, the memory module comprises a memory module substrate having a rectangular shape, a plurality of DRAMs arranged in a row in a longitudinal direction of the memory module substrate, a command/address buffer between the DRAMs, and a PLL chip which distributes clocks to the respective DRAMs, and the respective memory modules constitute a memory sub-system.
Here, each DRAM on the memory module extends in a short direction of the module substrate and is connected to a module data wiring, and the command/address buffer and a PLL chip are connected to a module command/address wiring and a module clock wiring extending in the short direction of the module substrate.
Furthermore, a module command/address distribution wiring and a module clock distribution wiring are drawn out in the longitudinal direction of the module substrate in order to distribute commands, addresses, and clocks to the respective DRAMs from the command/address buffer and PLL chip.
In this constitution, a data signal is directly transmitted to a DRAM chip on the memory module constituting each memory sub-system from the memory controller disposed on the mother board substrate, and a command/address signal and a clock signal are transmitted to the DRAM chip on each memory module via the command/address buffer and PLL chip from the memory controller.
According to this memory module constitution, even when a write and read rate with respect to the DRAM chip is lowered as compared with a transfer rate of the system data signal, the system data signal can be transferred to an external circuit at a high rate.
However, as described in Patent Document 1, it has become clear that a constitution in which a plurality of DRAM chips are arranged in a plane on a mounting substrate cannot meet a requirement for a high data rate of 12.8 GBps with respect to the memory module of the next generation.
On the other hand, in Japanese Patent Application Laid-Open No. 6-291250 (Patent Document 2), a semiconductor integrated circuit has been described including a constitution whose length and breadth are standardized and in which a plurality of IC chips comprising signal pads are stacked on standardized/unified positions and in which the pad of the IC chip is connected to another pad by a longitudinal wiring.
In Patent Document 2, as a concrete example, an example is described in which four layers of SRAMs are stacked on an address decoder layer (FIG. 8 and paragraph 0025). In this case, the address decoder layer is disposed as a first layer, and SRAM layers are disposed as second to fifth layers. Chip enable buses for individually selecting SRAMs are connected to the SRAMs disposed in the second to fifth layers. Accordingly, the respective SRMs are individual selected and activated.
In Patent Document 2, one of a plurality of SRAM layers is selected on the address decoder layer, and the data signal from the selected SRAM layer is output as it is to the outside from the address decoder layer.
Furthermore, in Japanese Patent Publication No. 9-504654 (Patent Document 3), a memory package has been described in which a single IC chip is replaced with an IC chip laminate, an interface circuit for translating a signal between a host system and the IC chip laminate is included in the IC chip laminate (claim 2). Even in this example, the stacked IC chip laminates are selectively controlled by an interface circuit so that the laminates operate independently of one another. In this case, a signal and transfer rate of the data signal between the host system and IC chip laminate are equal to those of an internal data signal inside the IC chip laminate.
In other words, in Cited Document 3, anything is not considered concerning a case where an internal data width inside the IC chip laminate is larger than a data signal width outside the IC chip laminate.
Moreover, a memory having a three-dimensional structure has been described in U.S. Pat. No. 6,133,640 (Patent Document 4). In Patent Document 4, a constitution is described in which memory circuits and a control logic circuit are individual arranged on a plurality of physically separated layers, the memory circuits of the respective layers are individually optimized by the single control logic circuit, accordingly the plurality of memory circuits are operated, and cost is reduced.
Among Patent Documents 1 to 4 described above, in Patent Documents 2 to 4, anything is not suggested with respect to the memory system and DRAM module (memory module) described in Patent Document 1. Furthermore, concerning the memory system in which the width and transfer speed of the data signal inside the module are different from those of the data signal outside the module and problems in the memory system, anything is not pointed out in Patent Documents 1 to 4 described above.
In the memory system described in Patent Document 1, data from the plurality of DRAMs are transmitted/received as memory sub-system data, and the plurality of DRAMs are arranged in a row in a plane on the module substrate.
However, it has become clear that with an increase of the number of DRAMs mounted on the module substrate in this memory sub-system, a demand for a higher speed, especially a demand for a high data rate of 12.8 GBps in the memory module of the next generation cannot be met.
As a result of intensive research of a cause for hindering the speeding-up in the above-described DRAM module by the present inventors, it has become that a wiring topology of a data signal, address command signal, and clock signal between the memory controller and each DRAM chip differs by several cm on the mounting substrate with the arrangement of a plurality of DRAM chips in a plane on the mounting substrate. Therefore, a difference is made in a signal reach time by this degree of difference of the wiring topology, that is, skew occurs, and it has become clear that this skew cannot be corrected even using PLL with an increase of the transfer rate.
Furthermore, there is a problem that when the transfer rate is raised, a consumption current in the memory sub-system accordingly increases. A DLL circuit for receiving/transmitting a high-frequency transmission signal is mounted on each DRAM chip on the memory module, the consumption current occupies about 15% of a read/write current at 800 Mbps, and this results in a circumstance in which an increase of consumption current cannot be avoided.
The above-described problem will be concretely described hereinafter with reference to FIG. 40.
The memory sub-system, that is, the memory module which is an object of the present invention will be schematically described with reference to FIG. 40. First, a memory module shown in FIG. 40 comprises a module substrate 200, a plurality of DRAM chips (nine chips) 701 arranged in a row in a plane on the module substrate 200, and a register 202, PLL 203, and serial presence detector (SPD) 204 arranged in a middle portion of the module substrate 200, and the module substrate 200 is attached onto a mother board (not shown) via a connector (not shown).
Here, in addition to the shown memory module, another memory module is mounted together with a chip set (memory controller) on the mother board, and these plurality of memory modules and the chip set constitute a memory system.
A module data wiring is laid below the respective DRAMs 201 in the drawing, that is, in a short direction of the module substrate 200. On the other hand, a module command/address wiring is disposed below the register 202 in the drawing. Furthermore, a module clock wiring extends below the PLL 203 in the drawing, and these module command/address wiring and module clock wiring are connected to a connector disposed in a longitudinal direction of the module substrate 200. The SPD 204 is a memory which determines an operation condition of the DRAM chip 201 mounted on the module substrate 200, and usually comprises ROM.
Furthermore, a module command/address distribution wiring is disposed for each DRAM chip 201 in the longitudinal direction of the module substrate 200, that is, in a transverse direction from the shown register 202, and a module clock distribution wiring is similarly disposed for each DRAM chip 201 from the PLL 203.
In the memory module including this constitution, data having a bit number in accordance with a bus width of a memory access data bus can be input/output as module data. However, in this constitution, a topology of a module data wiring is different from a topology of a module command distribution wiring from a module command wiring and topologies of the module clock wiring and module clock distribution wiring from the PLL 203.
On the other hand, in the shown memory module constitution, a method in which a broad bus width is used as means for realizing a data rate required by a processor (general data processing system using SDRAM such as DDR) and a method in which the transfer rate is raised with a small bus width (system of RDRAM) are used.
In these methods, for a conventional general memory module constituted with a large bus width, 4 to 16 single DRAMs having an IO number of 16, 8, 4 are mounted in a row in a plane on the module substrate to constitute 64 or 72 data buses.
On the other hand, the module command/address signal and module clock signal are usually shared by all the DRAM chips 201 on the module substrate 200. Therefore, for these wirings, as shown, the register 202 and PLL 203 are mounted on the module substrate 200, these register 202 and PLL 203 adjust timings for buffering and wiring delay on the module, and the module command/address signal and the module clock signal are supplied to each DRAM chip 201.
As described above, the data signal, address command signal, and clock signal distributed from the memory controller (chip set) have physically different wiring topologies, and transmission characteristics of the signal differ.
The difference of the signal reach time or the skew which cannot be corrected by the PLL 203 are generated by the difference of this physical wiring topology in the data signal, module clock signal, and command/address signal, and a problem occurs that this is a large obstacle in further raising the transfer rate.
Furthermore, as another problem in this type of memory system, there is a problem of a branch wiring on a data wiring caused because it is possible to additionally dispose the memory module. Usually, the module is increased by insertion/detachment with respect to a socket connected to the bus wiring. Therefore, the data signal is branched on the bus wiring and supplied to the DRAM chip 201 in the module. A problem occurs that an obstacle is brought in high-rate signal transmission by signal reflection caused by this branch wiring.
Moreover, when the memory module is increased, deterioration of a signal quality by the branch wiring or that of a signal quality by LC which is parasitic on a DRAM package increases. Therefore, the number of additional modules in DDRII using this constitution has a limitation of two slots in the actual circumstances. In actual, the data rate which can be realized in the memory sub-system by the DDRII using this constitution is 533 Mbps per data pin and about 4.26 GBps per system channel.
On the other hand, a method has also been proposed in which the transfer rate is raised with a small bus width in the memory module of a shown form (RDRAM). In this method, the single RDRAM having an IO number of 16 is connected in series on the bus wiring and disposed. Therefore, the data signal, module address/command signal, and module clock signal distributed from the memory controller have the physically same wiring topology, and the difference of the signal reach time in each RDRAM, that is, skew is not generated.
Moreover, since each RDRAM is mounted on the bus, the signal wiring is not branched.
Therefore, at present, the transfer rate of the bus which can be realized in the memory sub-system by the RDRAM using this constitution is 1.066 Gbps per data pin. However, since the data width is only two bytes, the data rate of the system is about 2.13 GBps. Furthermore, a method of constituting the system of two channels is used in order to raise the data rate of the memory system, but the rate is about 4.26 GBps even in this case.
In this constitution of the RDRAM, the bus is not branched, but 4 times or more RDRAMs need to be connected to the same bus in order to realize a required memory capacity. When a large number of RDRAMs are connected to a long bus in this manner, the deterioration of the signal quality by the LC parasitic on the RDRAM package increases. Therefore, a restriction is generated on addition of the memory capacity, and it is difficult to realize the memory capacity required for the system. It is difficult to realize a high required data rate in a state in which a large number of DRAMs as loads are connected and held onto a long bus.
Moreover, it is also considered that the IO number in the RDRAM is increased, but the RDRAM chips and packages increase, and the cost of the single RDRAM increases. When the IO number is increased in the same RDRAM, an accessible page size is reduced by an IO unit, and the requirement of the system is not satisfied.